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master
arturo182 8 months ago
commit
a2dfc21811
17 changed files with 2223 additions and 0 deletions
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      .gitignore
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      MIMXRT1011xxxxx_flexspi_nor.ld
  3. +104
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      Makefile
  4. +148
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      board.h
  5. +345
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      clock_config.c
  6. +104
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      clock_config.h
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      main.c
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      startup_mimxrt1011.c
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      tools/Flash/MIMXRT1010_SFDP_QSPI.cfx
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      tools/MIMXRT1011xxxxx.xml
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      tools/MIMXRT1011xxxxx_part.xml
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      tools/Scripts/RT1010_connect.scp
  13. +28
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      tools/Scripts/probetable.csv
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      tools/crt_common.xme
  15. BIN
      tools/crt_emu_cm_redlink
  16. BIN
      tools/libredlinkclient.so
  17. BIN
      tools/redlinkserv

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.gitignore View File

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out

+ 328
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MIMXRT1011xxxxx_flexspi_nor.ld View File

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/*
* GENERATED FILE - DO NOT EDIT
* Copyright (c) 2008-2013 Code Red Technologies Ltd,
* Copyright 2015, 2018-2019 NXP
* (c) NXP Semiconductors 2013-2019
* Generated linker script file for MIMXRT1011xxxxx
* Created from memory.ldt by FMCreateLinkMemory
* Using Freemarker v2.3.23
* MCUXpresso IDE v11.0.1 [Build 2563] [2019-09-01] on 24-Oct-2019 23:52:33
*/

MEMORY
{
/* Define each memory region */
BOARD_FLASH (rx) : ORIGIN = 0x60000000, LENGTH = 0x1000000 /* 16M bytes (alias Flash) */
SRAM_DTC (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM) */
SRAM_ITC (rwx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
SRAM_OC (rwx) : ORIGIN = 0x20200000, LENGTH = 0x10000 /* 64K bytes (alias RAM3) */
NCACHE_REGION (rwx) : ORIGIN = 0x20210000, LENGTH = 0x0 /* 0M bytes (alias RAM4) */
}

/* Define a symbol for the top of each memory region */
__base_BOARD_FLASH = 0x60000000 ; /* BOARD_FLASH */
__base_Flash = 0x60000000 ; /* Flash */
__top_BOARD_FLASH = 0x60000000 + 0x1000000 ; /* 16M bytes */
__top_Flash = 0x60000000 + 0x1000000 ; /* 16M bytes */
__base_SRAM_DTC = 0x20000000 ; /* SRAM_DTC */
__base_RAM = 0x20000000 ; /* RAM */
__top_SRAM_DTC = 0x20000000 + 0x8000 ; /* 32K bytes */
__top_RAM = 0x20000000 + 0x8000 ; /* 32K bytes */
__base_SRAM_ITC = 0x0 ; /* SRAM_ITC */
__base_RAM2 = 0x0 ; /* RAM2 */
__top_SRAM_ITC = 0x0 + 0x8000 ; /* 32K bytes */
__top_RAM2 = 0x0 + 0x8000 ; /* 32K bytes */
__base_SRAM_OC = 0x20200000 ; /* SRAM_OC */
__base_RAM3 = 0x20200000 ; /* RAM3 */
__top_SRAM_OC = 0x20200000 + 0x10000 ; /* 64K bytes */
__top_RAM3 = 0x20200000 + 0x10000 ; /* 64K bytes */
__base_NCACHE_REGION = 0x20210000 ; /* NCACHE_REGION */
__base_RAM4 = 0x20210000 ; /* RAM4 */
__top_NCACHE_REGION = 0x20210000 + 0x0 ; /* 0M bytes */
__top_RAM4 = 0x20210000 + 0x0 ; /* 0M bytes */


ENTRY(ResetISR)

SECTIONS
{
/* Image Vector Table and Boot Data for booting from external flash */
.boot_hdr : ALIGN(4)
{
FILL(0xff)
. = 0x400 ;
__boot_hdr_start__ = ABSOLUTE(.) ;
KEEP(*(.boot_hdr.conf))
. = 0x1000 ;
KEEP(*(.boot_hdr.ivt))
. = 0x1020 ;
KEEP(*(.boot_hdr.boot_data))
. = 0x1030 ;
KEEP(*(.boot_hdr.dcd_data))
__boot_hdr_end__ = ABSOLUTE(.) ;
. = 0x2000 ;
} >BOARD_FLASH

/* MAIN TEXT SECTION */
.text : ALIGN(4)
{
FILL(0xff)
__vectors_start__ = ABSOLUTE(.) ;
KEEP(*(.isr_vector))
/* Global Section Table */
. = ALIGN(4) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data));
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2));
LONG( SIZEOF(.data_RAM2));
LONG(LOADADDR(.data_RAM3));
LONG( ADDR(.data_RAM3));
LONG( SIZEOF(.data_RAM3));
LONG(LOADADDR(.data_RAM4));
LONG( ADDR(.data_RAM4));
LONG( SIZEOF(.data_RAM4));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
LONG( ADDR(.bss_RAM3));
LONG( SIZEOF(.bss_RAM3));
LONG( ADDR(.bss_RAM4));
LONG( SIZEOF(.bss_RAM4));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */

*(.after_vectors*)

} > BOARD_FLASH

.text : ALIGN(4)
{
*(.text*)
*(.rodata .rodata.* .constdata .constdata.*)
. = ALIGN(4);
} > BOARD_FLASH
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(4)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > BOARD_FLASH

__exidx_start = .;

.ARM.exidx : ALIGN(4)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > BOARD_FLASH
__exidx_end = .;

_etext = .;

/* DATA section for SRAM_ITC */

.data_RAM2 : ALIGN(4)
{
FILL(0xff)
PROVIDE(__start_data_RAM2 = .) ;
*(.ramfunc.$RAM2)
*(.ramfunc.$SRAM_ITC)
*(.data.$RAM2)
*(.data.$SRAM_ITC)
*(.data.$RAM2.*)
*(.data.$SRAM_ITC.*)
. = ALIGN(4) ;
PROVIDE(__end_data_RAM2 = .) ;
} > SRAM_ITC AT>BOARD_FLASH
/* DATA section for SRAM_OC */

.data_RAM3 : ALIGN(4)
{
FILL(0xff)
PROVIDE(__start_data_RAM3 = .) ;
*(.ramfunc.$RAM3)
*(.ramfunc.$SRAM_OC)
*(.data.$RAM3)
*(.data.$SRAM_OC)
*(.data.$RAM3.*)
*(.data.$SRAM_OC.*)
. = ALIGN(4) ;
PROVIDE(__end_data_RAM3 = .) ;
} > SRAM_OC AT>BOARD_FLASH
/* DATA section for NCACHE_REGION */

.data_RAM4 : ALIGN(4)
{
FILL(0xff)
PROVIDE(__start_data_RAM4 = .) ;
*(.ramfunc.$RAM4)
*(.ramfunc.$NCACHE_REGION)
*(.data.$RAM4)
*(.data.$NCACHE_REGION)
*(.data.$RAM4.*)
*(.data.$NCACHE_REGION.*)
. = ALIGN(4) ;
PROVIDE(__end_data_RAM4 = .) ;
} > NCACHE_REGION AT>BOARD_FLASH
/* MAIN DATA SECTION */
.uninit_RESERVED (NOLOAD) :
{
. = ALIGN(4) ;
KEEP(*(.bss.$RESERVED*))
. = ALIGN(4) ;
_end_uninit_RESERVED = .;
} > SRAM_DTC

/* Main DATA section (SRAM_DTC) */
.data : ALIGN(4)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
KEEP(*(CodeQuickAccess))
KEEP(*(DataQuickAccess))
*(RamFunction)
*(NonCacheable.init)
*(.data*)
. = ALIGN(4) ;
_edata = . ;
} > SRAM_DTC AT>BOARD_FLASH

/* BSS section for SRAM_ITC */
.bss_RAM2 :
{
. = ALIGN(4) ;
PROVIDE(__start_bss_RAM2 = .) ;
*(.bss.$RAM2)
*(.bss.$SRAM_ITC)
*(.bss.$RAM2.*)
*(.bss.$SRAM_ITC.*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM2 = .) ;
} > SRAM_ITC

/* BSS section for SRAM_OC */
.bss_RAM3 :
{
. = ALIGN(4) ;
PROVIDE(__start_bss_RAM3 = .) ;
*(.bss.$RAM3)
*(.bss.$SRAM_OC)
*(.bss.$RAM3.*)
*(.bss.$SRAM_OC.*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM3 = .) ;
} > SRAM_OC

/* BSS section for NCACHE_REGION */
.bss_RAM4 :
{
. = ALIGN(4) ;
PROVIDE(__start_bss_RAM4 = .) ;
*(.bss.$RAM4)
*(.bss.$NCACHE_REGION)
*(.bss.$RAM4.*)
*(.bss.$NCACHE_REGION.*)
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
PROVIDE(__end_bss_RAM4 = .) ;
} > NCACHE_REGION

/* MAIN BSS SECTION */
.bss :
{
. = ALIGN(4) ;
_bss = .;
*(NonCacheable)
*(.bss*)
*(COMMON)
. = ALIGN(4) ;
_ebss = .;
PROVIDE(end = .);
} > SRAM_DTC

/* NOINIT section for SRAM_ITC */
.noinit_RAM2 (NOLOAD) :
{
. = ALIGN(4) ;
*(.noinit.$RAM2)
*(.noinit.$SRAM_ITC)
*(.noinit.$RAM2.*)
*(.noinit.$SRAM_ITC.*)
. = ALIGN(4) ;
} > SRAM_ITC

/* NOINIT section for SRAM_OC */
.noinit_RAM3 (NOLOAD) :
{
. = ALIGN(4) ;
*(.noinit.$RAM3)
*(.noinit.$SRAM_OC)
*(.noinit.$RAM3.*)
*(.noinit.$SRAM_OC.*)
. = ALIGN(4) ;
} > SRAM_OC

/* NOINIT section for NCACHE_REGION */
.noinit_RAM4 (NOLOAD) :
{
. = ALIGN(4) ;
*(.noinit.$RAM4)
*(.noinit.$NCACHE_REGION)
*(.noinit.$RAM4.*)
*(.noinit.$NCACHE_REGION.*)
. = ALIGN(4) ;
} > NCACHE_REGION

/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD):
{
. = ALIGN(4) ;
_noinit = .;
*(.noinit*)
. = ALIGN(4) ;
_end_noinit = .;
} > SRAM_DTC

/* Reserve and place Heap within memory map */
_HeapSize = 0x800;
.heap : ALIGN(4)
{
_pvHeapStart = .;
. += _HeapSize;
. = ALIGN(4);
_pvHeapLimit = .;
} > SRAM_DTC

_StackSize = 0x800;
/* Reserve space in memory for Stack */
.heap2stackfill :
{
. += _StackSize;
} > SRAM_DTC
/* Locate actual Stack in memory map */
.stack ORIGIN(SRAM_DTC) + LENGTH(SRAM_DTC) - _StackSize - 0: ALIGN(4)
{
_vStackBase = .;
. = ALIGN(4);
_vStackTop = . + _StackSize;
} > SRAM_DTC

/* Provide basic symbols giving location and size of main text
* block, including initial values of RW data sections. Note that
* these will need extending to give a complete picture with
* complex images (e.g multiple Flash banks).
*/
_image_start = LOADADDR(.text);
_image_end = LOADADDR(.data) + SIZEOF(.data);
_image_size = _image_end - _image_start;
}

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Makefile View File

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CROSS_COMPILE ?= arm-none-eabi-
SDK_PATH ?= ..

CC := $(CROSS_COMPILE)gcc
LD := $(CROSS_COMPILE)ld
OBJCOPY := $(CROSS_COMPILE)objcopy
SIZE := $(CROSS_COMPILE)size

SRCS := \
main.c \
clock_config.c \
startup_mimxrt1011.c \
$(SDK_PATH)/boards/evkmimxrt1010/xip/evkmimxrt1010_flexspi_nor_config.c \
$(SDK_PATH)/devices/MIMXRT1011/drivers/fsl_clock.c \
$(SDK_PATH)/devices/MIMXRT1011/drivers/fsl_gpio.c \
$(SDK_PATH)/devices/MIMXRT1011/drivers/fsl_lpuart.c \
$(SDK_PATH)/devices/MIMXRT1011/system_MIMXRT1011.c \
$(SDK_PATH)/devices/MIMXRT1011/xip/fsl_flexspi_nor_boot.c \

INCS := \
. \
$(SDK_PATH)/devices/MIMXRT1011/utilities/debug_console \
$(SDK_PATH)/devices/MIMXRT1011/utilities/str \
$(SDK_PATH)/devices/MIMXRT1011/utilities \
$(SDK_PATH)/devices/MIMXRT1011/drivers \
$(SDK_PATH)/devices/MIMXRT1011 \
$(SDK_PATH)/CMSIS/Include

DEFS := \
CPU_MIMXRT1011DAE5A \
CPU_MIMXRT1011DAE5A_cm7 \
SDK_DEBUGCONSOLE=1 \
CR_INTEGER_PRINTF\
PRINTF_FLOAT_ENABLE=0\
__MCUXPRESSO\
__USE_CMSIS \
DEBUG \
XIP_EXTERNAL_FLASH=1 \
XIP_BOOT_HEADER_ENABLE=1 \
DEBUG_CONSOLE_RX_ENABLE=0

LIBS := -lm -lc -lgcc -lnosys

OBJS := $(patsubst %.c,out/obj/%.c.o, $(filter %.c, $(SRCS)))
DEPS := $(patsubst %.o,%.d,$(OBJS))
LDSCRIPT := MIMXRT1011xxxxx_flexspi_nor.ld

CFLAGS := \
-mcpu=cortex-m7 -mthumb -mapcs \
-mfloat-abi=hard -mfpu=fpv5-sp-d16 \
-std=gnu99 -Os -g3 -Wall -Wextra -Wno-unused-parameter \
-fno-common -ffunction-sections -fdata-sections -ffreestanding -fno-builtin -fstack-usage \
$(addprefix -D, $(DEFS)) \
$(addprefix -I, $(INCS))

LDFLAGS := \
-mcpu=cortex-m7 -mfloat-abi=hard -mfpu=fpv5-sp-d16 -mthumb -mapcs \
-Xlinker --sort-section=alignment -Xlinker --cref \
-Wl,--gc-sections --specs=nano.specs \
-T$(LDSCRIPT) \
$(LIBS)

all: out/app.bin
.PHONY: all

out/obj/%.c.o: %.c
@echo "CC $<"
@mkdir -p $(dir $@)
@$(CC) -MM -MF $(subst .o,.d,$@) -MP -MT "$@ $(subst .o,.d,$@)" $(CFLAGS) $<
@$(CC) $(CFLAGS) -c -o $@ $<

out/app.elf: $(OBJS)
@echo "LD $@"
@$(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) -Xlinker -Map=$@.map
@$(SIZE) $@

%.bin: %.elf
@$(OBJCOPY) -O binary $< $@

clean:
@echo "Removing the out directory"
@rm -rf out/
.PHONY: clean

flash: out/app.bin
@./tools/crt_emu_cm_redlink \
-p MIMXRT1011xxxxx \
--flash-load-exec "$<" \
--load-base=0x60000000 \
--connectscript=RT1010_connect.scp \
--debug 4 \
--no-packed
.PHONY: flash

debug: out/app.elf
@arm-none-eabi-gdb $< \
-ex "set non-stop on" \
-ex "target extended-remote | ./tools/crt_emu_cm_redlink -g -pMIMXRT1011xxxxx --connectscript=RT1010_connect.scp --no-packed" \
-ex "load"
.PHONY: debug

ifneq ("$(MAKECMDGOALS)","clean")
-include $(DEPS)
endif

+ 148
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board.h View File

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/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/

#ifndef _BOARD_H_
#define _BOARD_H_

//#include "clock_config.h"
#include "fsl_common.h"
//#include "fsl_gpio.h"
//
///*******************************************************************************
// * Definitions
// ******************************************************************************/
///*! @brief The board name */
//#define BOARD_NAME "MIMXRT1010-EVK"
//
///* The UART to use for debug messages. */
//#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
//#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
//#define BOARD_DEBUG_UART_INSTANCE 1U
//
//#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
//
//#define BOARD_UART_IRQ LPUART1_IRQn
//#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
//
//#ifndef BOARD_DEBUG_UART_BAUDRATE
//#define BOARD_DEBUG_UART_BAUDRATE (115200U)
//#endif /* BOARD_DEBUG_UART_BAUDRATE */
//
///* @Brief Board accelerator sensor configuration */
//#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
//#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
//#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
//#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
//
//#define BOARD_CODEC_I2C_BASEADDR LPI2C1
//#define BOARD_CODEC_I2C_INSTANCE 1U
//#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
//#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
//#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
//
///*! @brief The USER_LED used for board */
//#define LOGIC_LED_ON (0U)
//#define LOGIC_LED_OFF (1U)
//#ifndef BOARD_USER_LED_GPIO
//#define BOARD_USER_LED_GPIO GPIO1
//#endif
//#ifndef BOARD_USER_LED_GPIO_PIN
//#define BOARD_USER_LED_GPIO_PIN (11U)
//#endif
//
/*#define USER_LED_INIT(output) \
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN)
*/
//#define USER_LED_OFF() GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN)
//#define USER_LED_ON() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
/*#define USER_LED_TOGGLE() \
GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN))
*/

///*! @brief Define the port interrupt number for the board switches */
//#ifndef BOARD_USER_BUTTON_GPIO
//#define BOARD_USER_BUTTON_GPIO GPIO2
//#endif
//#ifndef BOARD_USER_BUTTON_GPIO_PIN
//#define BOARD_USER_BUTTON_GPIO_PIN (5U)
//#endif
//#define BOARD_USER_BUTTON_IRQ GPIO2_Combined_0_15_IRQn
//#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO2_Combined_0_15_IRQHandler
//#define BOARD_USER_BUTTON_NAME "SW4"
//
///*! @brief The flash size */
#define BOARD_FLASH_SIZE (0x1000000U)
//
///* USB PHY condfiguration */
//#define BOARD_USB_PHY_D_CAL (0x0CU)
//#define BOARD_USB_PHY_TXCAL45DP (0x06U)
//#define BOARD_USB_PHY_TXCAL45DM (0x06U)
//
//#define BOARD_ARDUINO_INT_IRQ (GPIO1_Combined_16_31_IRQn)
//#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
//#define BOARD_ARDUINO_I2C_INDEX (1)
//
///*! @brief The WIFI-QCA shield pin. */
//#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
//#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
//#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO_PIN 8U /*!< PIO1 pin index: 8 */
//#define BOARD_INITSILEX2401SHIELD_PWRON_PIN_NAME GPIO1_08 /*!< Pin name */
//#define BOARD_INITSILEX2401SHIELD_PWRON_LABEL "PWRON" /*!< Label */
//#define BOARD_INITSILEX2401SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
//#define BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
//
//#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
//#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
//#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 4U /*!< PIO1 pin index: 4 */
//#define BOARD_INITSILEX2401SHIELD_IRQ_PIN_NAME GPIO1_04 /*!< Pin name */
//#define BOARD_INITSILEX2401SHIELD_IRQ_LABEL "IRQ" /*!< Label */
//#define BOARD_INITSILEX2401SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
//#define BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
//
//#if defined(__cplusplus)
//extern "C" {
//#endif /* __cplusplus */
//
///*******************************************************************************
// * API
// ******************************************************************************/
//uint32_t BOARD_DebugConsoleSrcFreq(void);
//
//void BOARD_InitDebugConsole(void);
//void BOARD_ConfigMPU(void);
//#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
//void BOARD_InitDebugConsole(void);
//void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
//status_t BOARD_LPI2C_Send(LPI2C_Type *base,
// uint8_t deviceAddress,
// uint32_t subAddress,
// uint8_t subaddressSize,
// uint8_t *txBuff,
// uint8_t txBuffSize);
//status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
// uint8_t deviceAddress,
// uint32_t subAddress,
// uint8_t subaddressSize,
// uint8_t *rxBuff,
// uint8_t rxBuffSize);
//void BOARD_Accel_I2C_Init(void);
//status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
//status_t BOARD_Accel_I2C_Receive(
// uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
//void BOARD_Codec_I2C_Init(void);
//status_t BOARD_Codec_I2C_Send(
// uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
//status_t BOARD_Codec_I2C_Receive(
// uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
//#endif /* SDK_I2C_BASED_COMPONENT_USED */
//#if defined(__cplusplus)
//}
//#endif /* __cplusplus */

#endif /* _BOARD_H_ */

+ 345
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clock_config.c View File

@@ -0,0 +1,345 @@
/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/

/*
* How to setup clock using clock driver functions:
*
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
*
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
*
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
*
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
*
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
*
*/

/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v6.0
processor: MIMXRT1011xxxxx
package_id: MIMXRT1011DAE5A
mcu_data: ksdk2_0
processor_version: 0.0.1
board: MIMXRT1010-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/

#include "clock_config.h"
#include "fsl_iomuxc.h"

/*******************************************************************************
* Definitions
******************************************************************************/

/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;

/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void InitBootClocks(void)
{
BootClockRUN();
}

/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
settings:
- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
- {id: CCM.IPG_PODF.scale, value: '4'}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
- {id: CCM_ANALOG.PLL2.denom, value: '1'}
- {id: CCM_ANALOG.PLL2.div, value: '22'}
- {id: CCM_ANALOG.PLL2.num, value: '0'}
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
sources:
- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/

/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
.numerator = 0, /* 30 bit numerator of fractional loop divider */
.denominator = 1, /* 30 bit denominator of fractional loop divider */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = {
.enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
.src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BootClockRUN(void)
{
/* Init RTC OSC clock frequency. */
CLOCK_SetRtcXtalFreq(32768U);
/* Enable 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
/* Use free 1MHz clock output. */
XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
/* Set XTAL 24MHz clock frequency. */
CLOCK_SetXtalFreq(24000000U);
/* Enable XTAL 24MHz clock source. */
CLOCK_InitExternalClk(0);
/* Enable internal RC. */
CLOCK_InitRcOsc24M();
/* Switch clock source to external OSC. */
CLOCK_SwitchOsc(kCLOCK_XtalOsc);
/* Set Oscillator ready counter value. */
CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
/* Setting the VDD_SOC to 1.5V. It is necessary to config CORE to 500Mhz. */
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Disable IPG clock gate. */
CLOCK_DisableClock(kCLOCK_Adc1);
CLOCK_DisableClock(kCLOCK_Xbar1);
/* Set IPG_PODF. */
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
CLOCK_DisableClock(kCLOCK_Gpt2);
CLOCK_DisableClock(kCLOCK_Gpt2S);
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
* unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
* well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
/* Set FLEXSPI_PODF. */
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
/* Set Flexspi clock source. */
CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
#endif
/* Disable ADC_ACLK_EN clock gate. */
CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
/* Set ADC_ACLK_PODF. */
CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
/* Disable LPSPI clock gate. */
CLOCK_DisableClock(kCLOCK_Lpspi1);
CLOCK_DisableClock(kCLOCK_Lpspi2);
/* Set LPSPI_PODF. */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
/* Set Lpspi clock source. */
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
/* Set Trace clock source. */
CLOCK_SetMux(kCLOCK_TraceMux, 2);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
/* Set SAI1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
/* Set Sai1 clock source. */
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
/* Disable SAI3 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai3);
/* Set SAI3_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
/* Set SAI3_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
/* Set Sai3 clock source. */
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
/* Disable Lpi2c clock gate. */
CLOCK_DisableClock(kCLOCK_Lpi2c1);
CLOCK_DisableClock(kCLOCK_Lpi2c2);
/* Set LPI2C_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
/* Set Lpi2c clock source. */
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
/* Disable UART clock gate. */
CLOCK_DisableClock(kCLOCK_Lpuart1);
CLOCK_DisableClock(kCLOCK_Lpuart2);
CLOCK_DisableClock(kCLOCK_Lpuart3);
CLOCK_DisableClock(kCLOCK_Lpuart4);
/* Set UART_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
/* Set Uart clock source. */
CLOCK_SetMux(kCLOCK_UartMux, 0);
/* Disable SPDIF clock gate. */
CLOCK_DisableClock(kCLOCK_Spdif);
/* Set SPDIF0_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
/* Set SPDIF0_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
/* Set Spdif clock source. */
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
/* Disable Flexio1 clock gate. */
CLOCK_DisableClock(kCLOCK_Flexio1);
/* Set FLEXIO1_CLK_PRED. */
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
/* Set FLEXIO1_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
/* Set Flexio1 clock source. */
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
/* Set Pll3 sw clock source. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
* unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
* well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
/* Disable Usb1 PLL output for USBPHY1. */
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* Init Enet PLL. */
CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
/* Set clock out2 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
/* Set clock out2 source. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
/* Set clock out1 drives clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
/* Disable clock out1. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}

+ 104
- 0
clock_config.h View File

@@ -0,0 +1,104 @@
/*
* Copyright 2019 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/

#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_

#include "fsl_common.h"

/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */

#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/

#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/

/*!
* @brief This function executes default configuration of clocks.
*
*/
void InitBootClocks(void);

#if defined(__cplusplus)
}
#endif /* __cplusplus*/

/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */

/* Clock outputs (values are in Hz): */
#define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
#define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL
#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
#define BOARD_BOOTCLOCKRUN_USBPHY_CLK 0UL

/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
*/
extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;

/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/

/*!
* @brief This function executes configuration of clocks.
*
*/
void BootClockRUN(void);

#if defined(__cplusplus)
}
#endif /* __cplusplus*/

#endif /* _CLOCK_CONFIG_H_ */

+ 236
- 0
main.c View File

@@ -0,0 +1,236 @@
#include <stdio.h>

#include "clock_config.h"

#include "fsl_gpio.h"
#include "fsl_lpuart.h"
#include "fsl_iomuxc.h"

void InitPins(void)
{
/* iomuxc clock (iomuxc_clk_enable): 0x03U */
CLOCK_EnableClock(kCLOCK_Iomuxc);

/* GPIO_SD_05 is configured as GPIO2_IO05 */
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0U);

/* GPIO_09 is configured as LPUART1_RXD */
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0U);

/* GPIO_10 is configured as LPUART1_TXD */
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0U);

/* GPIO_11 is configured as GPIOMUX_IO11 */
/* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(IOMUXC_GPIO_11_GPIOMUX_IO11, 0U);

/* GPIO_SD_05 PAD functional properties : */
/* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/4
Speed Field: fast(150MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Enabled */
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0x01B0A0U);

/* GPIO_09 PAD functional properties : */
/* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: fast(150MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(IOMUXC_GPIO_09_LPUART1_RXD, 0x10B0U);

/* GPIO_10 PAD functional properties : */
/* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/4
Speed Field: fast(150MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(IOMUXC_GPIO_10_LPUART1_TXD, 0x10A0U);

/* GPIO_11 PAD functional properties : */
/* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/4
Speed Field: fast(150MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 47K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(IOMUXC_GPIO_11_GPIOMUX_IO11, 0x70A0U);
}

void ConfigMPU(void)
{
extern uint32_t __base_NCACHE_REGION;
extern uint32_t __top_NCACHE_REGION;
uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
uint32_t i = 0;

/* Disable I cache and D cache */
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) {
SCB_DisableICache();
}
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) {
SCB_DisableDCache();
}

/* Disable MPU */
ARM_MPU_Disable();

/* MPU configure:
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
* SubRegionDisable, Size)
* API in mpu_armv7.h.
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
* disabled.
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
* Privileged mode.
* Use MACROS defined in mpu_armv7.h:
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
* 0 x 0 0 Strongly Ordered shareable
* 0 x 0 1 Device shareable
* 0 0 1 0 Normal not shareable Outer and inner write
* through no write allocate
* 0 0 1 1 Normal not shareable Outer and inner write
* back no write allocate
* 0 1 1 0 Normal shareable Outer and inner write
* through no write allocate
* 0 1 1 1 Normal shareable Outer and inner write
* back no write allocate
* 1 0 0 0 Normal not shareable outer and inner
* noncache
* 1 1 0 0 Normal shareable outer and inner
* noncache
* 1 0 1 1 Normal not shareable outer and inner write
* back write/read acllocate
* 1 1 1 1 Normal shareable outer and inner write
* back write/read acllocate
* 2 x 0 0 Device not shareable
* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
* policy.
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
* mpu_armv7.h.
*/

/* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(0, 0x80000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);

/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(1, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);

#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
/* Region 2 setting: Memory with Normal type, not shareable, outer/inner write back. */
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
#endif

/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);

/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32KB);

/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32KB);

/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);

while ((size >> i) > 0x1U) {
i++;
}

if (i != 0) {
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
assert(!(nonCacheStart % size));
assert(size == (uint32_t)(1 << i));
assert(i >= 5);

/* Region 7 setting: Memory with Normal type, not shareable, non-cacheable */
MPU->RBAR = ARM_MPU_RBAR(7, nonCacheStart);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
}

/* Enable MPU */
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);

/* Enable I cache and D cache */
SCB_EnableDCache();
SCB_EnableICache();
}

uint32_t DebugConsoleSrcFreq(void)
{
uint32_t freq;

/* To make it simple, we assume default PLL and divider settings, and the only variable
from application is use PLL3 source or OSC source */
/* PLL3 div6 80M */
if (CLOCK_GetMux(kCLOCK_UartMux) == 0) {
freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
} else {
freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
}

return freq;
}

int _write(void *fd, const char *msg, size_t len)
{
LPUART_WriteBlocking(LPUART1, (uint8_t*)msg, len);

return len;
}

int main(void)
{
ConfigMPU();
InitPins();
BootClockRUN();

gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0, kGPIO_NoIntmode };
gpio_pin_config_t sw_config = { kGPIO_DigitalInput, 0, kGPIO_NoIntmode };
lpuart_config_t config;

LPUART_GetDefaultConfig(&config);
config.baudRate_Bps = 115200;
config.enableTx = true;
config.enableRx = true;

LPUART_Init(LPUART1, &config, DebugConsoleSrcFreq());

printf("Hello World!\r\n");

GPIO_PinInit(GPIO1, 11, &led_config);
GPIO_PinInit(GPIO2, 5, &sw_config);

while (1) {
GPIO_PinWrite(GPIO1, 11, GPIO_PinRead(GPIO2, 5));
//LPUART_ReadBlocking(LPUART1, &ch, 1);
//LPUART_WriteBlocking(LPUART1, &ch, 1);
}
}

+ 865
- 0
startup_mimxrt1011.c View File

@@ -0,0 +1,865 @@
//*****************************************************************************
// MIMXRT1011 startup code for use with MCUXpresso IDE
//
// Version : 120419
//*****************************************************************************
//
// Copyright 2016-2019 NXP
// All rights reserved.
//
// SPDX-License-Identifier: BSD-3-Clause
//*****************************************************************************

#if defined (DEBUG)
#pragma GCC push_options
#pragma GCC optimize ("Og")
#endif // (DEBUG)

#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif

#define WEAK __attribute__ ((weak))
#define WEAK_AV __attribute__ ((weak, section(".after_vectors")))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))

//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif

//*****************************************************************************
// Variable to store CRP value in. Will be placed automatically
// by the linker when "Enable Code Read Protect" selected.
// See crp.h header for more information
//*****************************************************************************
//*****************************************************************************
// Declaration of external SystemInit function
//*****************************************************************************
#if defined (__USE_CMSIS)
extern void SystemInit(void);
#endif // (__USE_CMSIS)

//*****************************************************************************
// Forward declaration of the core exception handlers.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions.
// If your application is a C++ one, then any interrupt handlers defined
// in C++ files within in your main application will need to have C linkage
// rather than C++ linkage. To do this, make sure that you are using extern "C"
// { .... } around the interrupt handler within your main application code.
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);

//*****************************************************************************
// Forward declaration of the application IRQ handlers. When the application
// defines a handler (with the same name), this will automatically take
// precedence over weak definitions below
//*****************************************************************************
WEAK void DMA0_IRQHandler(void);
WEAK void DMA1_IRQHandler(void);
WEAK void DMA2_IRQHandler(void);
WEAK void DMA3_IRQHandler(void);
WEAK void DMA4_IRQHandler(void);
WEAK void DMA5_IRQHandler(void);
WEAK void DMA6_IRQHandler(void);
WEAK void DMA7_IRQHandler(void);
WEAK void DMA8_IRQHandler(void);
WEAK void DMA9_IRQHandler(void);
WEAK void DMA10_IRQHandler(void);
WEAK void DMA11_IRQHandler(void);
WEAK void DMA12_IRQHandler(void);
WEAK void DMA13_IRQHandler(void);
WEAK void DMA14_IRQHandler(void);
WEAK void DMA15_IRQHandler(void);
WEAK void DMA_ERROR_IRQHandler(void);
WEAK void CTI0_ERROR_IRQHandler(void);
WEAK void CTI1_ERROR_IRQHandler(void);
WEAK void CORE_IRQHandler(void);
WEAK void LPUART1_IRQHandler(void);
WEAK void LPUART2_IRQHandler(void);
WEAK void LPUART3_IRQHandler(void);
WEAK void LPUART4_IRQHandler(void);
WEAK void PIT_IRQHandler(void);
WEAK void USB_OTG1_IRQHandler(void);
WEAK void FLEXSPI_IRQHandler(void);
WEAK void FLEXRAM_IRQHandler(void);
WEAK void LPI2C1_IRQHandler(void);
WEAK void LPI2C2_IRQHandler(void);
WEAK void GPT1_IRQHandler(void);
WEAK void GPT2_IRQHandler(void);
WEAK void LPSPI1_IRQHandler(void);
WEAK void LPSPI2_IRQHandler(void);
WEAK void PWM1_0_IRQHandler(void);
WEAK void PWM1_1_IRQHandler(void);
WEAK void PWM1_2_IRQHandler(void);
WEAK void PWM1_3_IRQHandler(void);
WEAK void PWM1_FAULT_IRQHandler(void);
WEAK void KPP_IRQHandler(void);
WEAK void SRC_IRQHandler(void);
WEAK void GPR_IRQ_IRQHandler(void);
WEAK void CCM_1_IRQHandler(void);
WEAK void CCM_2_IRQHandler(void);
WEAK void EWM_IRQHandler(void);
WEAK void WDOG2_IRQHandler(void);
WEAK void SNVS_HP_WRAPPER_IRQHandler(void);
WEAK void SNVS_HP_WRAPPER_TZ_IRQHandler(void);
WEAK void SNVS_LP_WRAPPER_IRQHandler(void);
WEAK void CSU_IRQHandler(void);
WEAK void DCP_IRQHandler(void);
WEAK void DCP_VMI_IRQHandler(void);
WEAK void Reserved68_IRQHandler(void);
WEAK void TRNG_IRQHandler(void);
WEAK void Reserved70_IRQHandler(void);
WEAK void Reserved71_IRQHandler(void);
WEAK void SAI1_IRQHandler(void);
WEAK void RTWDOG_IRQHandler(void);
WEAK void SAI3_RX_IRQHandler(void);
WEAK void SAI3_TX_IRQHandler(void);
WEAK void SPDIF_IRQHandler(void);
WEAK void PMU_IRQHandler(void);
WEAK void XBAR1_IRQ_0_1_2_3_IRQHandler(void);
WEAK void TEMP_LOW_HIGH_IRQHandler(void);
WEAK void TEMP_PANIC_IRQHandler(void);
WEAK void USB_PHY_IRQHandler(void);
WEAK void GPC_IRQHandler(void);
WEAK void ADC1_IRQHandler(void);
WEAK void FLEXIO1_IRQHandler(void);
WEAK void DCDC_IRQHandler(void);
WEAK void GPIO1_Combined_0_15_IRQHandler(void);
WEAK void GPIO1_Combined_16_31_IRQHandler(void);
WEAK void GPIO2_Combined_0_15_IRQHandler(void);
WEAK void GPIO5_Combined_0_15_IRQHandler(void);
WEAK void WDOG1_IRQHandler(void);
WEAK void ADC_ETC_IRQ0_IRQHandler(void);
WEAK void ADC_ETC_IRQ1_IRQHandler(void);
WEAK void ADC_ETC_IRQ2_IRQHandler(void);
WEAK void ADC_ETC_IRQ3_IRQHandler(void);
WEAK void ADC_ETC_ERROR_IRQ_IRQHandler(void);

//*****************************************************************************
// Forward declaration of the driver IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the driver
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//*****************************************************************************
void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA8_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA9_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA10_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA11_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA12_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA13_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA14_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA15_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CTI0_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CTI1_ERROR_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CORE_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPUART1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPUART2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPUART3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPUART4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PIT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void USB_OTG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void FLEXSPI_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void FLEXRAM_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPI2C1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPI2C2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPSPI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void LPSPI2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_FAULT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void KPP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SRC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPR_IRQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CCM_1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CCM_2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void EWM_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void WDOG2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SNVS_HP_WRAPPER_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SNVS_HP_WRAPPER_TZ_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SNVS_LP_WRAPPER_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void CSU_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DCP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DCP_VMI_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void Reserved68_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void TRNG_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void Reserved70_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void Reserved71_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SAI1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void RTWDOG_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SAI3_RX_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SAI3_TX_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void SPDIF_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void PMU_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void XBAR1_IRQ_0_1_2_3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void TEMP_LOW_HIGH_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void TEMP_PANIC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void USB_PHY_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void FLEXIO1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void DCDC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO1_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO1_Combined_16_31_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO2_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO5_Combined_0_15_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void WDOG1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_ETC_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_ETC_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_ETC_IRQ2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_ETC_IRQ3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_ETC_ERROR_IRQ_DriverIRQHandler(void) ALIAS(IntDefaultHandler);

//*****************************************************************************
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);

//*****************************************************************************
// External declaration for the pointer to the stack top from the Linker Script
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
// The vector table.
// This relies on the linker script to place at correct location in memory.
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
extern void * __Vectors __attribute__ ((alias ("g_pfnVectors")));

__attribute__ ((used, section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM7
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
0, // Reserved
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler

// Chip Level - MIMXRT1011
DMA0_IRQHandler, // 16: DMA channel 0 transfer complete
DMA1_IRQHandler, // 17: DMA channel 1 transfer complete
DMA2_IRQHandler, // 18: DMA channel 2 transfer complete
DMA3_IRQHandler, // 19: DMA channel 3 transfer complete
DMA4_IRQHandler, // 20: DMA channel 4 transfer complete
DMA5_IRQHandler, // 21: DMA channel 5 transfer complete
DMA6_IRQHandler, // 22: DMA channel 6 transfer complete
DMA7_IRQHandler, // 23: DMA channel 7 transfer complete
DMA8_IRQHandler, // 24: DMA channel 8 transfer complete
DMA9_IRQHandler, // 25: DMA channel 9 transfer complete
DMA10_IRQHandler, // 26: DMA channel 10 transfer complete
DMA11_IRQHandler, // 27: DMA channel 11 transfer complete
DMA12_IRQHandler, // 28: DMA channel 12 transfer complete
DMA13_IRQHandler, // 29: DMA channel 13 transfer complete
DMA14_IRQHandler, // 30: DMA channel 14 transfer complete
DMA15_IRQHandler, // 31: DMA channel 15 transfer complete
DMA_ERROR_IRQHandler, // 32: DMA error interrupt channels 0-15
CTI0_ERROR_IRQHandler, // 33: CTI trigger outputs
CTI1_ERROR_IRQHandler, // 34: CTI trigger outputs
CORE_IRQHandler, // 35: CorePlatform exception IRQ
LPUART1_IRQHandler, // 36: LPUART1 TX interrupt and RX interrupt
LPUART2_IRQHandler, // 37: LPUART2 TX interrupt and RX interrupt
LPUART3_IRQHandler, // 38: LPUART3 TX interrupt and RX interrupt
LPUART4_IRQHandler, // 39: LPUART4 TX interrupt and RX interrupt
PIT_IRQHandler, // 40: PIT interrupt
USB_OTG1_IRQHandler, // 41: USBO2 USB OTG1
FLEXSPI_IRQHandler, // 42: FlexSPI0 interrupt
FLEXRAM_IRQHandler, // 43: FlexRAM address out of range Or access hit IRQ
LPI2C1_IRQHandler, // 44: LPI2C1 interrupt
LPI2C2_IRQHandler, // 45: LPI2C2 interrupt
GPT1_IRQHandler, // 46: GPT1 interrupt
GPT2_IRQHandler, // 47: GPT2 interrupt
LPSPI1_IRQHandler, // 48: LPSPI1 single interrupt vector for all sources
LPSPI2_IRQHandler, // 49: LPSPI2 single interrupt vector for all sources
PWM1_0_IRQHandler, // 50: PWM1 capture 0, compare 0, or reload 0 interrupt
PWM1_1_IRQHandler, // 51: PWM1 capture 1, compare 1, or reload 0 interrupt
PWM1_2_IRQHandler, // 52: PWM1 capture 2, compare 2, or reload 0 interrupt
PWM1_3_IRQHandler, // 53: PWM1 capture 3, compare 3, or reload 0 interrupt
PWM1_FAULT_IRQHandler, // 54: PWM1 fault or reload error interrupt
KPP_IRQHandler, // 55: Keypad nterrupt
SRC_IRQHandler, // 56: SRC interrupt
GPR_IRQ_IRQHandler, // 57: Used to notify cores on exception condition while boot
CCM_1_IRQHandler, // 58: CCM IRQ1 interrupt
CCM_2_IRQHandler, // 59: CCM IRQ2 interrupt
EWM_IRQHandler, // 60: EWM interrupt
WDOG2_IRQHandler, // 61: WDOG2 interrupt
SNVS_HP_WRAPPER_IRQHandler, // 62: SNVS Functional Interrupt
SNVS_HP_WRAPPER_TZ_IRQHandler, // 63: SNVS Security Interrupt
SNVS_LP_WRAPPER_IRQHandler, // 64: ON-OFF button press shorter than 5 secs (pulse event)
CSU_IRQHandler, // 65: CSU interrupt
DCP_IRQHandler, // 66: Combined DCP channel interrupts(except channel 0) and CRC interrupt
DCP_VMI_IRQHandler, // 67: IRQ of DCP channel 0
Reserved68_IRQHandler, // 68: Reserved interrupt
TRNG_IRQHandler, // 69: TRNG interrupt
Reserved70_IRQHandler, // 70: Reserved interrupt
Reserved71_IRQHandler, // 71: Reserved interrupt
SAI1_IRQHandler, // 72: SAI1 interrupt
RTWDOG_IRQHandler, // 73: RTWDOG interrupt
SAI3_RX_IRQHandler, // 74: SAI3 interrupt
SAI3_TX_IRQHandler, // 75: SAI3 interrupt
SPDIF_IRQHandler, // 76: SPDIF interrupt
PMU_IRQHandler, // 77: PMU interrupt
XBAR1_IRQ_0_1_2_3_IRQHandler, // 78: XBAR1 interrupt
TEMP_LOW_HIGH_IRQHandler, // 79: TEMPMON interrupt
TEMP_PANIC_IRQHandler, // 80: TEMPMON interrupt
USB_PHY_IRQHandler, // 81: USBPHY (OTG1 UTMI), Interrupt
GPC_IRQHandler, // 82: GPC interrupt
ADC1_IRQHandler, // 83: ADC1 interrupt
FLEXIO1_IRQHandler, // 84: FLEXIO1 interrupt
DCDC_IRQHandler, // 85: DCDC interrupt
GPIO1_Combined_0_15_IRQHandler, // 86: Combined interrupt indication for GPIO1 signal 0 throughout 15
GPIO1_Combined_16_31_IRQHandler, // 87: Combined interrupt indication for GPIO1 signal 16 throughout 31
GPIO2_Combined_0_15_IRQHandler, // 88: Combined interrupt indication for GPIO2 signal 0 throughout 15
GPIO5_Combined_0_15_IRQHandler, // 89: Combined interrupt indication for GPIO5 signal 0 throughout 15
WDOG1_IRQHandler, // 90: WDOG1 interrupt
ADC_ETC_IRQ0_IRQHandler, // 91: ADCETC IRQ0 interrupt
ADC_ETC_IRQ1_IRQHandler, // 92: ADCETC IRQ1 interrupt
ADC_ETC_IRQ2_IRQHandler, // 93: ADCETC IRQ2 interrupt
ADC_ETC_IRQ3_IRQHandler, // 94: ADCETC IRQ3 interrupt
ADC_ETC_ERROR_IRQ_IRQHandler, // 95: ADCETC Error IRQ interrupt

}; /* End of g_pfnVectors */

//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors.init_data")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}

__attribute__ ((section(".after_vectors.init_bss")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}

//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;

//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
__attribute__ ((section(".after_vectors.reset")))
void ResetISR(void) {

// Disable interrupts
__asm volatile ("cpsid i");


#if defined (__USE_CMSIS)
// If __USE_CMSIS defined, then call CMSIS SystemInit code
SystemInit();
#else
// Disable Watchdog
volatile unsigned int *WDOG1_WCR = (unsigned int *) 0x400B8000;
*WDOG1_WCR = *WDOG1_WCR & ~(1 << 2);
volatile unsigned int *WDOG2_WCR = (unsigned int *) 0x400D0000;
*WDOG2_WCR = *WDOG2_WCR & ~(1 << 2);
// Write watchdog update key to unlock
*((volatile unsigned int *)0x400BC004) = 0xD928C520;
// Set timeout value
*((volatile unsigned int *)0x400BC008) = 0xFFFF;
// Now disable watchdog via control register
volatile unsigned int *RTWDOG_CS = (unsigned int *) 0x400BC000;
*RTWDOG_CS = (*RTWDOG_CS & ~(1 << 7)) | (1 << 5);

#endif // (__USE_CMSIS)

//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;

// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;

// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}

// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}


#if !defined (__USE_CMSIS)
// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
// will setup the VTOR register

// Check to see if we are running the code from a non-zero
// address (eg RAM, external flash), in which case we need
// to modify the VTOR register to tell the CPU that the
// vector table is located at a non-0x0 address.
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
*pSCB_VTOR = (unsigned int)g_pfnVectors;
}
#endif // (__USE_CMSIS)
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif

// Reenable interrupts
__asm volatile ("cpsie i");

#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main();
#else
main();
#endif

//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}

//*****************************************************************************
// Default core exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
WEAK_AV void NMI_Handler(void)
{ while(1) {}
}

WEAK_AV void HardFault_Handler(void)
{ while(1) {}
}

WEAK_AV void SVC_Handler(void)
{ while(1) {}
}

WEAK_AV void PendSV_Handler(void)
{ while(1) {}
}

WEAK_AV void SysTick_Handler(void)
{ while(1) {}
}

//*****************************************************************************
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//*****************************************************************************
WEAK_AV void IntDefaultHandler(void)
{ while(1) {}
}

//*****************************************************************************
// Default application exception handlers. Override the ones here by defining
// your own handler routines in your application code. These routines call
// driver exception handlers or IntDefaultHandler() if no driver exception
// handler is included.
//*****************************************************************************
WEAK void DMA0_IRQHandler(void)
{ DMA0_DriverIRQHandler();
}

WEAK void DMA1_IRQHandler(void)
{ DMA1_DriverIRQHandler();
}

WEAK void DMA2_IRQHandler(void)
{ DMA2_DriverIRQHandler();
}

WEAK void DMA3_IRQHandler(void)
{ DMA3_DriverIRQHandler();
}

WEAK void DMA4_IRQHandler(void)
{ DMA4_DriverIRQHandler();
}

WEAK void DMA5_IRQHandler(void)
{ DMA5_DriverIRQHandler();
}

WEAK void DMA6_IRQHandler(void)
{ DMA6_DriverIRQHandler();
}

WEAK void DMA7_IRQHandler(void)
{ DMA7_DriverIRQHandler();
}

WEAK void DMA8_IRQHandler(void)
{ DMA8_DriverIRQHandler();
}

WEAK void DMA9_IRQHandler(void)
{ DMA9_DriverIRQHandler();
}

WEAK void DMA10_IRQHandler(void)
{ DMA10_DriverIRQHandler();
}

WEAK void DMA11_IRQHandler(void)
{ DMA11_DriverIRQHandler();
}

WEAK void DMA12_IRQHandler(void)
{ DMA12_DriverIRQHandler();
}

WEAK void DMA13_IRQHandler(void)
{ DMA13_DriverIRQHandler();
}

WEAK void DMA14_IRQHandler(void)
{ DMA14_DriverIRQHandler();
}

WEAK void DMA15_IRQHandler(void)
{ DMA15_DriverIRQHandler();
}

WEAK void DMA_ERROR_IRQHandler(void)
{ DMA_ERROR_DriverIRQHandler();
}

WEAK void CTI0_ERROR_IRQHandler(void)
{ CTI0_ERROR_DriverIRQHandler();
}

WEAK void CTI1_ERROR_IRQHandler(void)
{ CTI1_ERROR_DriverIRQHandler();
}

WEAK void CORE_IRQHandler(void)
{ CORE_DriverIRQHandler();
}

WEAK void LPUART1_IRQHandler(void)
{ LPUART1_DriverIRQHandler();
}

WEAK void LPUART2_IRQHandler(void)
{ LPUART2_DriverIRQHandler();
}

WEAK void LPUART3_IRQHandler(void)
{ LPUART3_DriverIRQHandler();
}

WEAK void LPUART4_IRQHandler(void)
{ LPUART4_DriverIRQHandler();
}

WEAK void PIT_IRQHandler(void)
{ PIT_DriverIRQHandler();
}

WEAK void USB_OTG1_IRQHandler(void)
{ USB_OTG1_DriverIRQHandler();
}

WEAK void FLEXSPI_IRQHandler(void)
{ FLEXSPI_DriverIRQHandler();
}

WEAK void FLEXRAM_IRQHandler(void)
{ FLEXRAM_DriverIRQHandler();
}

WEAK void LPI2C1_IRQHandler(void)
{ LPI2C1_DriverIRQHandler();
}

WEAK void LPI2C2_IRQHandler(void)
{ LPI2C2_DriverIRQHandler();
}

WEAK void GPT1_IRQHandler(void)
{ GPT1_DriverIRQHandler();
}

WEAK void GPT2_IRQHandler(void)
{ GPT2_DriverIRQHandler();
}

WEAK void LPSPI1_IRQHandler(void)
{ LPSPI1_DriverIRQHandler();
}

WEAK void LPSPI2_IRQHandler(void)
{ LPSPI2_DriverIRQHandler();
}

WEAK void PWM1_0_IRQHandler(void)
{ PWM1_0_DriverIRQHandler();
}

WEAK void PWM1_1_IRQHandler(void)
{ PWM1_1_DriverIRQHandler();
}

WEAK void PWM1_2_IRQHandler(void)
{ PWM1_2_DriverIRQHandler();
}

WEAK void PWM1_3_IRQHandler(void)
{ PWM1_3_DriverIRQHandler();
}

WEAK void PWM1_FAULT_IRQHandler(void)
{ PWM1_FAULT_DriverIRQHandler();
}

WEAK void KPP_IRQHandler(void)
{ KPP_DriverIRQHandler();
}

WEAK void SRC_IRQHandler(void)
{ SRC_DriverIRQHandler();
}

WEAK void GPR_IRQ_IRQHandler(void)
{ GPR_IRQ_DriverIRQHandler();
}

WEAK void CCM_1_IRQHandler(void)
{ CCM_1_DriverIRQHandler();
}

WEAK void CCM_2_IRQHandler(void)
{ CCM_2_DriverIRQHandler();
}

WEAK void EWM_IRQHandler(void)
{ EWM_DriverIRQHandler();
}

WEAK void WDOG2_IRQHandler(void)
{ WDOG2_DriverIRQHandler();
}

WEAK void SNVS_HP_WRAPPER_IRQHandler(void)
{ SNVS_HP_WRAPPER_DriverIRQHandler();
}

WEAK void SNVS_HP_WRAPPER_TZ_IRQHandler(void)
{ SNVS_HP_WRAPPER_TZ_DriverIRQHandler();
}

WEAK void SNVS_LP_WRAPPER_IRQHandler(void)
{ SNVS_LP_WRAPPER_DriverIRQHandler();
}

WEAK void CSU_IRQHandler(void)
{ CSU_DriverIRQHandler();
}

WEAK void DCP_IRQHandler(void)
{ DCP_DriverIRQHandler();
}

WEAK void DCP_VMI_IRQHandler(void)
{ DCP_VMI_DriverIRQHandler();
}

WEAK void Reserved68_IRQHandler(void)
{ Reserved68_DriverIRQHandler();
}

WEAK void TRNG_IRQHandler(void)
{ TRNG_DriverIRQHandler();
}

WEAK void Reserved70_IRQHandler(void)
{ Reserved70_DriverIRQHandler();
}

WEAK void Reserved71_IRQHandler(void)
{ Reserved71_DriverIRQHandler();
}

WEAK void SAI1_IRQHandler(void)
{ SAI1_DriverIRQHandler();
}

WEAK void RTWDOG_IRQHandler(void)
{ RTWDOG_DriverIRQHandler();
}

WEAK void SAI3_RX_IRQHandler(void)
{ SAI3_RX_DriverIRQHandler();
}

WEAK void SAI3_TX_IRQHandler(void)
{ SAI3_TX_DriverIRQHandler();
}

WEAK void SPDIF_IRQHandler(void)
{ SPDIF_DriverIRQHandler();
}

WEAK void PMU_IRQHandler(void)
{ PMU_DriverIRQHandler();
}

WEAK void XBAR1_IRQ_0_1_2_3_IRQHandler(void)
{ XBAR1_IRQ_0_1_2_3_DriverIRQHandler();
}

WEAK void TEMP_LOW_HIGH_IRQHandler(void)
{ TEMP_LOW_HIGH_DriverIRQHandler();
}

WEAK void TEMP_PANIC_IRQHandler(void)
{ TEMP_PANIC_DriverIRQHandler();
}

WEAK void USB_PHY_IRQHandler(void)
{ USB_PHY_DriverIRQHandler();
}

WEAK void GPC_IRQHandler(void)
{ GPC_DriverIRQHandler();
}

WEAK void ADC1_IRQHandler(void)
{ ADC1_DriverIRQHandler();
}

WEAK void FLEXIO1_IRQHandler(void)
{ FLEXIO1_DriverIRQHandler();
}

WEAK void DCDC_IRQHandler(void)
{ DCDC_DriverIRQHandler();
}

WEAK void GPIO1_Combined_0_15_IRQHandler(void)
{ GPIO1_Combined_0_15_DriverIRQHandler();
}

WEAK void GPIO1_Combined_16_31_IRQHandler(void)
{ GPIO1_Combined_16_31_DriverIRQHandler();
}

WEAK void GPIO2_Combined_0_15_IRQHandler(void)
{ GPIO2_Combined_0_15_DriverIRQHandler();
}

WEAK void GPIO5_Combined_0_15_IRQHandler(void)
{ GPIO5_Combined_0_15_DriverIRQHandler();
}

WEAK void WDOG1_IRQHandler(void)
{ WDOG1_DriverIRQHandler();
}

WEAK void ADC_ETC_IRQ0_IRQHandler(void)
{ ADC_ETC_IRQ0_DriverIRQHandler();
}

WEAK void ADC_ETC_IRQ1_IRQHandler(void)
{ ADC_ETC_IRQ1_DriverIRQHandler();
}

WEAK void ADC_ETC_IRQ2_IRQHandler(void)
{ ADC_ETC_IRQ2_DriverIRQHandler();
}

WEAK void ADC_ETC_IRQ3_IRQHandler(void)
{ ADC_ETC_IRQ3_DriverIRQHandler();
}

WEAK void ADC_ETC_ERROR_IRQ_IRQHandler(void)
{ ADC_ETC_ERROR_IRQ_DriverIRQHandler();
}

//*****************************************************************************

#if defined (DEBUG)
#pragma GCC pop_options
#endif // (DEBUG)

BIN
tools/Flash/MIMXRT1010_SFDP_QSPI.cfx View File


+ 5
- 0
tools/MIMXRT1011xxxxx.xml View File

@@ -0,0 +1,5 @@
<directory>
<chips chipVendor='NXP' >
<chip name='MIMXRT1011xxxxx' xml_file='MIMXRT1011xxxxx_part.xml' />
</chips>
</directory>

+ 22
- 0
tools/MIMXRT1011xxxxx_part.xml View File

@@ -0,0 +1,22 @@
<?xml version="1.0" encoding="UTF-8"?>
<infoList vendor="NXP">
<