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  1. /*
  2. * Copyright 2019 NXP
  3. * All rights reserved.
  4. *
  5. * SPDX-License-Identifier: BSD-3-Clause
  6. */
  7. /*
  8. * How to setup clock using clock driver functions:
  9. *
  10. * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
  11. *
  12. * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
  13. *
  14. * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
  15. *
  16. * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
  17. *
  18. * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
  19. *
  20. */
  21. /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
  22. !!GlobalInfo
  23. product: Clocks v6.0
  24. processor: MIMXRT1011xxxxx
  25. package_id: MIMXRT1011DAE5A
  26. mcu_data: ksdk2_0
  27. processor_version: 0.0.1
  28. board: MIMXRT1010-EVK
  29. * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
  30. #include "clock_config.h"
  31. #include "fsl_iomuxc.h"
  32. /*******************************************************************************
  33. * Definitions
  34. ******************************************************************************/
  35. /*******************************************************************************
  36. * Variables
  37. ******************************************************************************/
  38. /* System clock frequency. */
  39. extern uint32_t SystemCoreClock;
  40. /*******************************************************************************
  41. ************************ BOARD_InitBootClocks function ************************
  42. ******************************************************************************/
  43. void InitBootClocks(void)
  44. {
  45. BootClockRUN();
  46. }
  47. /*******************************************************************************
  48. ********************** Configuration BOARD_BootClockRUN ***********************
  49. ******************************************************************************/
  50. /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
  51. !!Configuration
  52. name: BOARD_BootClockRUN
  53. called_from_default_init: true
  54. outputs:
  55. - {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
  56. - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
  57. - {id: CLK_1M.outFreq, value: 1 MHz}
  58. - {id: CLK_24M.outFreq, value: 24 MHz}
  59. - {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
  60. - {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
  61. - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
  62. - {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
  63. - {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
  64. - {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
  65. - {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
  66. - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
  67. - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
  68. - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
  69. - {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
  70. - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
  71. - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
  72. - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
  73. - {id: SAI1_MCLK3.outFreq, value: 30 MHz}
  74. - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
  75. - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
  76. - {id: SAI3_MCLK3.outFreq, value: 30 MHz}
  77. - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
  78. - {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
  79. - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
  80. settings:
  81. - {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
  82. - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
  83. - {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
  84. - {id: CCM.IPG_PODF.scale, value: '4'}
  85. - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
  86. - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
  87. - {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
  88. - {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
  89. - {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
  90. - {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
  91. - {id: CCM_ANALOG.PLL2.denom, value: '1'}
  92. - {id: CCM_ANALOG.PLL2.div, value: '22'}
  93. - {id: CCM_ANALOG.PLL2.num, value: '0'}
  94. - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
  95. - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
  96. - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
  97. - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
  98. - {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
  99. - {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
  100. - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
  101. - {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
  102. - {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
  103. - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
  104. - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
  105. - {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
  106. - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
  107. - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
  108. - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
  109. - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
  110. - {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
  111. - {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
  112. - {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
  113. - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
  114. sources:
  115. - {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
  116. - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
  117. * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
  118. /*******************************************************************************
  119. * Variables for BOARD_BootClockRUN configuration
  120. ******************************************************************************/
  121. const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
  122. .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
  123. .numerator = 0, /* 30 bit numerator of fractional loop divider */
  124. .denominator = 1, /* 30 bit denominator of fractional loop divider */
  125. .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
  126. };
  127. const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
  128. .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
  129. .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
  130. };
  131. const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = {
  132. .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
  133. .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
  134. };
  135. /*******************************************************************************
  136. * Code for BOARD_BootClockRUN configuration
  137. ******************************************************************************/
  138. void BootClockRUN(void)
  139. {
  140. /* Init RTC OSC clock frequency. */
  141. CLOCK_SetRtcXtalFreq(32768U);
  142. /* Enable 1MHz clock output. */
  143. XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
  144. /* Use free 1MHz clock output. */
  145. XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
  146. /* Set XTAL 24MHz clock frequency. */
  147. CLOCK_SetXtalFreq(24000000U);
  148. /* Enable XTAL 24MHz clock source. */
  149. CLOCK_InitExternalClk(0);
  150. /* Enable internal RC. */
  151. CLOCK_InitRcOsc24M();
  152. /* Switch clock source to external OSC. */
  153. CLOCK_SwitchOsc(kCLOCK_XtalOsc);
  154. /* Set Oscillator ready counter value. */
  155. CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
  156. /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
  157. CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
  158. CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
  159. /* Setting the VDD_SOC to 1.5V. It is necessary to config CORE to 500Mhz. */
  160. DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
  161. /* Waiting for DCDC_STS_DC_OK bit is asserted */
  162. while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
  163. {
  164. }
  165. /* Set AHB_PODF. */
  166. CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
  167. /* Disable IPG clock gate. */
  168. CLOCK_DisableClock(kCLOCK_Adc1);
  169. CLOCK_DisableClock(kCLOCK_Xbar1);
  170. /* Set IPG_PODF. */
  171. CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
  172. /* Disable PERCLK clock gate. */
  173. CLOCK_DisableClock(kCLOCK_Gpt1);
  174. CLOCK_DisableClock(kCLOCK_Gpt1S);
  175. CLOCK_DisableClock(kCLOCK_Gpt2);
  176. CLOCK_DisableClock(kCLOCK_Gpt2S);
  177. CLOCK_DisableClock(kCLOCK_Pit);
  178. /* Set PERCLK_PODF. */
  179. CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
  180. /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
  181. * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
  182. * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
  183. * well.*/
  184. #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
  185. /* Disable Flexspi clock gate. */
  186. CLOCK_DisableClock(kCLOCK_FlexSpi);
  187. /* Set FLEXSPI_PODF. */
  188. CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
  189. /* Set Flexspi clock source. */
  190. CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
  191. CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
  192. #endif
  193. /* Disable ADC_ACLK_EN clock gate. */
  194. CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
  195. /* Set ADC_ACLK_PODF. */
  196. CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
  197. /* Disable LPSPI clock gate. */
  198. CLOCK_DisableClock(kCLOCK_Lpspi1);
  199. CLOCK_DisableClock(kCLOCK_Lpspi2);
  200. /* Set LPSPI_PODF. */
  201. CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
  202. /* Set Lpspi clock source. */
  203. CLOCK_SetMux(kCLOCK_LpspiMux, 2);
  204. /* Disable TRACE clock gate. */
  205. CLOCK_DisableClock(kCLOCK_Trace);
  206. /* Set TRACE_PODF. */
  207. CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
  208. /* Set Trace clock source. */
  209. CLOCK_SetMux(kCLOCK_TraceMux, 2);
  210. /* Disable SAI1 clock gate. */
  211. CLOCK_DisableClock(kCLOCK_Sai1);
  212. /* Set SAI1_CLK_PRED. */
  213. CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
  214. /* Set SAI1_CLK_PODF. */
  215. CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
  216. /* Set Sai1 clock source. */
  217. CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
  218. /* Disable SAI3 clock gate. */
  219. CLOCK_DisableClock(kCLOCK_Sai3);
  220. /* Set SAI3_CLK_PRED. */
  221. CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
  222. /* Set SAI3_CLK_PODF. */
  223. CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
  224. /* Set Sai3 clock source. */
  225. CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
  226. /* Disable Lpi2c clock gate. */
  227. CLOCK_DisableClock(kCLOCK_Lpi2c1);
  228. CLOCK_DisableClock(kCLOCK_Lpi2c2);
  229. /* Set LPI2C_CLK_PODF. */
  230. CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
  231. /* Set Lpi2c clock source. */
  232. CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
  233. /* Disable UART clock gate. */
  234. CLOCK_DisableClock(kCLOCK_Lpuart1);
  235. CLOCK_DisableClock(kCLOCK_Lpuart2);
  236. CLOCK_DisableClock(kCLOCK_Lpuart3);
  237. CLOCK_DisableClock(kCLOCK_Lpuart4);
  238. /* Set UART_CLK_PODF. */
  239. CLOCK_SetDiv(kCLOCK_UartDiv, 0);
  240. /* Set Uart clock source. */
  241. CLOCK_SetMux(kCLOCK_UartMux, 0);
  242. /* Disable SPDIF clock gate. */
  243. CLOCK_DisableClock(kCLOCK_Spdif);
  244. /* Set SPDIF0_CLK_PRED. */
  245. CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
  246. /* Set SPDIF0_CLK_PODF. */
  247. CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
  248. /* Set Spdif clock source. */
  249. CLOCK_SetMux(kCLOCK_SpdifMux, 3);
  250. /* Disable Flexio1 clock gate. */
  251. CLOCK_DisableClock(kCLOCK_Flexio1);
  252. /* Set FLEXIO1_CLK_PRED. */
  253. CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
  254. /* Set FLEXIO1_CLK_PODF. */
  255. CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
  256. /* Set Flexio1 clock source. */
  257. CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
  258. /* Set Pll3 sw clock source. */
  259. CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
  260. /* Init System PLL. */
  261. CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
  262. /* Init System pfd0. */
  263. CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
  264. /* Init System pfd1. */
  265. CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
  266. /* Init System pfd2. */
  267. CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
  268. /* Init System pfd3. */
  269. CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
  270. /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
  271. * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
  272. * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
  273. * well.*/
  274. #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
  275. /* Init Usb1 PLL. */
  276. CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
  277. /* Init Usb1 pfd0. */
  278. CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
  279. /* Init Usb1 pfd1. */
  280. CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
  281. /* Init Usb1 pfd2. */
  282. CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
  283. /* Init Usb1 pfd3. */
  284. CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
  285. /* Disable Usb1 PLL output for USBPHY1. */
  286. CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
  287. #endif
  288. /* DeInit Audio PLL. */
  289. CLOCK_DeinitAudioPll();
  290. /* Bypass Audio PLL. */
  291. CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
  292. /* Set divider for Audio PLL. */
  293. CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
  294. CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
  295. /* Enable Audio PLL output. */
  296. CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
  297. /* Init Enet PLL. */
  298. CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
  299. /* Set preperiph clock source. */
  300. CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
  301. /* Set periph clock source. */
  302. CLOCK_SetMux(kCLOCK_PeriphMux, 0);
  303. /* Set periph clock2 clock source. */
  304. CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
  305. /* Set per clock source. */
  306. CLOCK_SetMux(kCLOCK_PerclkMux, 0);
  307. /* Set clock out1 divider. */
  308. CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
  309. /* Set clock out1 source. */
  310. CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
  311. /* Set clock out2 divider. */
  312. CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
  313. /* Set clock out2 source. */
  314. CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
  315. /* Set clock out1 drives clock out1. */
  316. CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
  317. /* Disable clock out1. */
  318. CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
  319. /* Disable clock out2. */
  320. CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
  321. /* Set SAI1 MCLK1 clock source. */
  322. IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
  323. /* Set SAI1 MCLK2 clock source. */
  324. IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
  325. /* Set SAI1 MCLK3 clock source. */
  326. IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
  327. /* Set SAI3 MCLK3 clock source. */
  328. IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
  329. /* Set MQS configuration. */
  330. IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
  331. /* Set GPT1 High frequency reference clock source. */
  332. IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
  333. /* Set GPT2 High frequency reference clock source. */
  334. IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
  335. /* Set SystemCoreClock variable. */
  336. SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
  337. }