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  1. #include <stdio.h>
  2. #include "clock_config.h"
  3. #include "fsl_gpio.h"
  4. #include "fsl_lpuart.h"
  5. #include "fsl_iomuxc.h"
  6. void InitPins(void)
  7. {
  8. /* iomuxc clock (iomuxc_clk_enable): 0x03U */
  9. CLOCK_EnableClock(kCLOCK_Iomuxc);
  10. /* GPIO_SD_05 is configured as GPIO2_IO05 */
  11. /* Software Input On Field: Input Path is determined by functionality */
  12. IOMUXC_SetPinMux(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0U);
  13. /* GPIO_09 is configured as LPUART1_RXD */
  14. /* Software Input On Field: Input Path is determined by functionality */
  15. IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0U);
  16. /* GPIO_10 is configured as LPUART1_TXD */
  17. /* Software Input On Field: Input Path is determined by functionality */
  18. IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0U);
  19. /* GPIO_11 is configured as GPIOMUX_IO11 */
  20. /* Software Input On Field: Input Path is determined by functionality */
  21. IOMUXC_SetPinMux(IOMUXC_GPIO_11_GPIOMUX_IO11, 0U);
  22. /* GPIO_SD_05 PAD functional properties : */
  23. /* Slew Rate Field: Slow Slew Rate
  24. Drive Strength Field: R0/4
  25. Speed Field: fast(150MHz)
  26. Open Drain Enable Field: Open Drain Disabled
  27. Pull / Keep Enable Field: Pull/Keeper Enabled
  28. Pull / Keep Select Field: Pull
  29. Pull Up / Down Config. Field: 100K Ohm Pull Up
  30. Hyst. Enable Field: Hysteresis Enabled */
  31. IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0x01B0A0U);
  32. /* GPIO_09 PAD functional properties : */
  33. /* Slew Rate Field: Slow Slew Rate
  34. Drive Strength Field: R0/6
  35. Speed Field: fast(150MHz)
  36. Open Drain Enable Field: Open Drain Disabled
  37. Pull / Keep Enable Field: Pull/Keeper Enabled
  38. Pull / Keep Select Field: Keeper
  39. Pull Up / Down Config. Field: 100K Ohm Pull Down
  40. Hyst. Enable Field: Hysteresis Disabled */
  41. IOMUXC_SetPinConfig(IOMUXC_GPIO_09_LPUART1_RXD, 0x10B0U);
  42. /* GPIO_10 PAD functional properties : */
  43. /* Slew Rate Field: Slow Slew Rate
  44. Drive Strength Field: R0/4
  45. Speed Field: fast(150MHz)
  46. Open Drain Enable Field: Open Drain Disabled
  47. Pull / Keep Enable Field: Pull/Keeper Enabled
  48. Pull / Keep Select Field: Keeper
  49. Pull Up / Down Config. Field: 100K Ohm Pull Down
  50. Hyst. Enable Field: Hysteresis Disabled */
  51. IOMUXC_SetPinConfig(IOMUXC_GPIO_10_LPUART1_TXD, 0x10A0U);
  52. /* GPIO_11 PAD functional properties : */
  53. /* Slew Rate Field: Slow Slew Rate
  54. Drive Strength Field: R0/4
  55. Speed Field: fast(150MHz)
  56. Open Drain Enable Field: Open Drain Disabled
  57. Pull / Keep Enable Field: Pull/Keeper Enabled
  58. Pull / Keep Select Field: Pull
  59. Pull Up / Down Config. Field: 47K Ohm Pull Up
  60. Hyst. Enable Field: Hysteresis Disabled */
  61. IOMUXC_SetPinConfig(IOMUXC_GPIO_11_GPIOMUX_IO11, 0x70A0U);
  62. }
  63. void ConfigMPU(void)
  64. {
  65. #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
  66. extern uint32_t Image$$RW_m_ncache$$Base[];
  67. /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
  68. extern uint32_t Image$$RW_m_ncache_unused$$Base[];
  69. extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
  70. uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
  71. uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
  72. 0 :
  73. ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
  74. #elif defined(__MCUXPRESSO)
  75. extern uint32_t __base_NCACHE_REGION;
  76. extern uint32_t __top_NCACHE_REGION;
  77. uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
  78. uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
  79. #elif defined(__ICCARM__) || defined(__GNUC__)
  80. extern uint32_t __NCACHE_REGION_START[];
  81. extern uint32_t __NCACHE_REGION_SIZE[];
  82. uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
  83. uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
  84. #endif
  85. uint32_t i = 0;
  86. /* Disable I cache and D cache */
  87. if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) {
  88. SCB_DisableICache();
  89. }
  90. if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) {
  91. SCB_DisableDCache();
  92. }
  93. /* Disable MPU */
  94. ARM_MPU_Disable();
  95. /* MPU configure:
  96. * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
  97. * SubRegionDisable, Size)
  98. * API in mpu_armv7.h.
  99. * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
  100. * disabled.
  101. * param AccessPermission Data access permissions, allows you to configure read/write access for User and
  102. * Privileged mode.
  103. * Use MACROS defined in mpu_armv7.h:
  104. * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
  105. * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
  106. * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
  107. * 0 x 0 0 Strongly Ordered shareable
  108. * 0 x 0 1 Device shareable
  109. * 0 0 1 0 Normal not shareable Outer and inner write
  110. * through no write allocate
  111. * 0 0 1 1 Normal not shareable Outer and inner write
  112. * back no write allocate
  113. * 0 1 1 0 Normal shareable Outer and inner write
  114. * through no write allocate
  115. * 0 1 1 1 Normal shareable Outer and inner write
  116. * back no write allocate
  117. * 1 0 0 0 Normal not shareable outer and inner
  118. * noncache
  119. * 1 1 0 0 Normal shareable outer and inner
  120. * noncache
  121. * 1 0 1 1 Normal not shareable outer and inner write
  122. * back write/read acllocate
  123. * 1 1 1 1 Normal shareable outer and inner write
  124. * back write/read acllocate
  125. * 2 x 0 0 Device not shareable
  126. * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
  127. * policy.
  128. * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
  129. * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
  130. * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
  131. * mpu_armv7.h.
  132. */
  133. /* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
  134. MPU->RBAR = ARM_MPU_RBAR(0, 0x80000000U);
  135. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
  136. /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
  137. MPU->RBAR = ARM_MPU_RBAR(1, 0x60000000U);
  138. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
  139. #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
  140. /* Region 2 setting: Memory with Normal type, not shareable, outer/inner write back. */
  141. MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
  142. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
  143. #endif
  144. /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
  145. MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
  146. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
  147. /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
  148. MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
  149. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32KB);
  150. /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
  151. MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
  152. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32KB);
  153. /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
  154. MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
  155. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
  156. while ((size >> i) > 0x1U) {
  157. i++;
  158. }
  159. if (i != 0) {
  160. /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
  161. assert(!(nonCacheStart % size));
  162. assert(size == (uint32_t)(1 << i));
  163. assert(i >= 5);
  164. /* Region 7 setting: Memory with Normal type, not shareable, non-cacheable */
  165. MPU->RBAR = ARM_MPU_RBAR(7, nonCacheStart);
  166. MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
  167. }
  168. /* Enable MPU */
  169. ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
  170. /* Enable I cache and D cache */
  171. SCB_EnableDCache();
  172. SCB_EnableICache();
  173. }
  174. uint32_t DebugConsoleSrcFreq(void)
  175. {
  176. uint32_t freq;
  177. /* To make it simple, we assume default PLL and divider settings, and the only variable
  178. from application is use PLL3 source or OSC source */
  179. /* PLL3 div6 80M */
  180. if (CLOCK_GetMux(kCLOCK_UartMux) == 0) {
  181. freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
  182. } else {
  183. freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
  184. }
  185. return freq;
  186. }
  187. int _write(void *fd, const char *msg, size_t len)
  188. {
  189. LPUART_WriteBlocking(LPUART1, (uint8_t*)msg, len);
  190. return len;
  191. }
  192. int main(void)
  193. {
  194. ConfigMPU();
  195. InitPins();
  196. BootClockRUN();
  197. gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0, kGPIO_NoIntmode };
  198. gpio_pin_config_t sw_config = { kGPIO_DigitalInput, 0, kGPIO_NoIntmode };
  199. lpuart_config_t config;
  200. LPUART_GetDefaultConfig(&config);
  201. config.baudRate_Bps = 115200;
  202. config.enableTx = true;
  203. config.enableRx = true;
  204. LPUART_Init(LPUART1, &config, DebugConsoleSrcFreq());
  205. printf("Hello World!\r\n");
  206. GPIO_PinInit(GPIO1, 11, &led_config);
  207. GPIO_PinInit(GPIO2, 5, &sw_config);
  208. while (1) {
  209. GPIO_PinWrite(GPIO1, 11, GPIO_PinRead(GPIO2, 5));
  210. //LPUART_ReadBlocking(LPUART1, &ch, 1);
  211. //LPUART_WriteBlocking(LPUART1, &ch, 1);
  212. }
  213. }