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230 lines
4.6 KiB

EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A3 16535 11693
encoding utf-8
Sheet 1 9
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 10250 4050 1250 250
U 5B86E669
F0 "L-network" 50
F1 "L-network.sch" 50
F2 "ant_in" I L 10250 4200 50
F3 "ant_out" O R 11500 4100 50
F4 "relay_inductor_[0..6]" I L 10250 4100 50
$EndSheet
$Sheet
S 10250 5300 1250 300
U 5B8756AD
F0 "C-network" 50
F1 "C-network.sch" 50
F2 "ant_cap" I L 10250 5400 50
F3 "relay_cap[0..6]" I L 10250 5500 50
$EndSheet
$Sheet
S 8650 4150 1250 350
U 5B8F98A6
F0 "diode-detector" 50
F1 "diode-detector.sch" 50
F2 "ant_in" I L 8650 4350 50
F3 "ant_out" O R 9900 4450 50
F4 "vrefl" O R 9900 4250 50
F5 "vfwd" O R 9900 4350 50
$EndSheet
Wire Wire Line
9900 4450 10150 4450
Wire Wire Line
10250 4200 10150 4200
Wire Wire Line
10150 4700 10250 4700
Wire Wire Line
11500 4100 11650 4100
Wire Wire Line
11650 4700 11500 4700
Wire Wire Line
11650 4400 12000 4400
Wire Wire Line
10250 4900 10150 4900
Wire Wire Line
10150 4900 10150 5400
Wire Wire Line
10150 5400 10250 5400
Connection ~ 10150 4450
Wire Wire Line
10150 4450 10150 4700
Wire Wire Line
10150 4200 10150 4450
Wire Wire Line
8650 4350 8450 4350
$Comp
L Connector:Conn_Coaxial J1
U 1 1 5B912871
P 8250 4350
F 0 "J1" V 8487 4280 50 0000 C CNN
F 1 "Conn_Coaxial" V 8396 4280 50 0000 C CNN
F 2 "xil_conn:BNC_SMD_Female" H 8250 4350 50 0001 C CNN
F 3 " ~" H 8250 4350 50 0001 C CNN
1 8250 4350
-1 0 0 -1
$EndComp
$Comp
L power:GND #PWR01
U 1 1 5B912D58
P 8250 4550
F 0 "#PWR01" H 8250 4300 50 0001 C CNN
F 1 "GND" H 8255 4377 50 0000 C CNN
F 2 "" H 8250 4550 50 0001 C CNN
F 3 "" H 8250 4550 50 0001 C CNN
1 8250 4550
1 0 0 -1
$EndComp
Wire Wire Line
11650 4100 11650 4400
$Comp
L Connector:Conn_Coaxial J2
U 1 1 5B914249
P 12200 4400
F 0 "J2" V 12437 4330 50 0000 C CNN
F 1 "Conn_Coaxial" V 12346 4330 50 0000 C CNN
F 2 "xil_conn:BNC_SMD_Female" H 12200 4400 50 0001 C CNN
F 3 " ~" H 12200 4400 50 0001 C CNN
1 12200 4400
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR02
U 1 1 5B914250
P 12200 4600
F 0 "#PWR02" H 12200 4350 50 0001 C CNN
F 1 "GND" H 12205 4427 50 0000 C CNN
F 2 "" H 12200 4600 50 0001 C CNN
F 3 "" H 12200 4600 50 0001 C CNN
1 12200 4600
-1 0 0 -1
$EndComp
Wire Wire Line
11650 4400 11650 4700
Connection ~ 11650 4400
$Sheet
S 8400 2550 1500 450
U 5B914F95
F0 "relay-controler" 50
F1 "relay-controler.sch" 50
F2 "relay_cap_[0..6]" O R 9900 2950 50
F3 "relay_inductor_[0..6]" O R 9900 2750 50
F4 "lc_switch" O R 9900 2850 50
F5 "SDA" I L 8400 2700 50
F6 "SCL" I L 8400 2800 50
$EndSheet
Wire Bus Line
10150 4100 10250 4100
Wire Bus Line
9900 2950 10050 2950
Wire Bus Line
10050 2950 10050 5500
Wire Bus Line
10050 5500 10250 5500
Wire Wire Line
10100 2850 10100 4800
Wire Wire Line
10100 4800 10250 4800
Wire Bus Line
9900 2750 10150 2750
Wire Bus Line
10150 2750 10150 4100
Wire Wire Line
10100 2850 9900 2850
$Sheet
S 4700 1700 900 200
U 5B94C7FF
F0 "power" 50
F1 "power.sch" 50
$EndSheet
$Sheet
S 6500 2200 1250 1000
U 5B94C806
F0 "MCU" 50
F1 "MCU.sch" 50
F2 "SDA" O R 7750 2700 50
F3 "SCL" O R 7750 2800 50
F4 "UART_TX" B L 6500 2650 50
F5 "UART_RX" B L 6500 2750 50
F6 "VREFL" I L 6500 3050 50
F7 "VFWD" I L 6500 2950 50
F8 "SWDIO" B L 6500 2550 50
F9 "SWCLK" B L 6500 2450 50
F10 "GPIO_[0..7]" B L 6500 2850 50
F11 "USB_D-" I L 6500 2250 50
F12 "USB_D+" I L 6500 2350 50
$EndSheet
Wire Wire Line
7750 2700 8400 2700
Wire Wire Line
7750 2800 8400 2800
$Sheet
S 10250 4650 1250 300
U 5B8F6DD2
F0 "lc-switch" 50
F1 "lc-switch.sch" 50
F2 "ant_in" I L 10250 4700 50
F3 "ant_out" O R 11500 4700 50
F4 "ant_cap" I L 10250 4900 50
F5 "lc_switch" I L 10250 4800 50
$EndSheet
Wire Wire Line
9900 4250 9950 4250
Wire Wire Line
9950 4250 9950 3700
Wire Wire Line
9950 3700 6400 3700
Wire Wire Line
6400 3700 6400 3050
Wire Wire Line
6400 3050 6500 3050
Wire Wire Line
6500 2950 6350 2950
Wire Wire Line
6350 2950 6350 3800
Wire Wire Line
6350 3800 10000 3800
Wire Wire Line
10000 3800 10000 4350
Wire Wire Line
10000 4350 9900 4350
$Sheet
S 4700 2150 900 900
U 5B91B43E
F0 "iopins" 50
F1 "iopins.sch" 50
F2 "GPIO_[0..7]" B R 5600 2850 50
F3 "SWCLK" B R 5600 2450 50
F4 "SWDIO" B R 5600 2550 50
F5 "UART_RX" B R 5600 2750 50
F6 "UART_TX" B R 5600 2650 50
F7 "USB_D+" I R 5600 2350 50
F8 "USB_D-" I R 5600 2250 50
$EndSheet
Wire Wire Line
6500 2450 5600 2450
Wire Wire Line
5600 2550 6500 2550
Wire Wire Line
6500 2650 5600 2650
Wire Wire Line
6500 2750 5600 2750
Wire Bus Line
5600 2850 6500 2850
Wire Wire Line
5600 2250 6500 2250
Wire Wire Line
6500 2350 5600 2350
$EndSCHEMATC