|Konrad Beckmann d07d8ea7d1 Fix clock domain constraints||4 days ago|
|3rdparty||4 months ago|
|gateware||1 week ago|
|hardware||5 months ago|
|openocd||5 months ago|
|rayman||4 months ago|
|software||4 days ago|
|.gitignore||4 months ago|
|LICENSE.txt||4 months ago|
|README.md||3 months ago|
This repo is a work in progress and far from release-worthy. Please don’t make your own boards and expect any kind of support. However, it might reach a stable point sometime in the future (as of 2019-01).
Kilsyth is a piece of hardware that contains an FPGA (Lattice ECP5) and a SuperSpeed USB 3.0 FIFO-bridge (FT60x). The goal is to provide a platform to be able to transfer high speed data transfers between a PC and an FPGA. The FPGA in turn can do whatever - e.g. interface with SDR, video capture, act as a logic analyzer.
It’s still in the early bring-up phase. Initial verification shows that it actually seems to work.
RevA is the first prototype and has been designed and built.
Ideas for RevB are still being collected. Feel free to suggest changes in an issue.
Requires a patched migen and a patched ftdi library.. Nasty, I know, sorry.
Help: $ python -m software.kilsyth -h Run blinky: $ python -m software.kilsyth run blinky
Reach out to @kbeckmann on Twitter or IRC/Freenode.