ECP5 FPGA + FT60x FIFO
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242 lines
3.6 KiB

  1. update=Tue 28 May 2019 11:57:29 PM CEST
  2. version=1
  3. last_client=kicad
  4. [general]
  5. version=1
  6. RootSch=
  7. BoardNm=
  8. [cvpcb]
  9. version=1
  10. NetIExt=net
  11. [eeschema]
  12. version=1
  13. LibDir=
  14. [eeschema/libraries]
  15. [pcbnew]
  16. version=1
  17. PageLayoutDescrFile=
  18. LastNetListRead=
  19. CopperLayerCount=4
  20. BoardThickness=1.6
  21. AllowMicroVias=0
  22. AllowBlindVias=0
  23. RequireCourtyardDefinitions=0
  24. ProhibitOverlappingCourtyards=1
  25. MinTrackWidth=0.08889999999999999
  26. MinViaDiameter=0.45
  27. MinViaDrill=0.2
  28. MinMicroViaDiameter=0.2
  29. MinMicroViaDrill=0.09999999999999999
  30. MinHoleToHole=0.25
  31. TrackWidth1=0.1524
  32. TrackWidth2=0.1524
  33. ViaDiameter1=0.8
  34. ViaDrill1=0.4
  35. dPairWidth1=0.2
  36. dPairGap1=0.25
  37. dPairViaGap1=0.25
  38. dPairWidth2=0.1524
  39. dPairGap2=0.127
  40. dPairViaGap2=0.127
  41. SilkLineWidth=0.12
  42. SilkTextSizeV=1
  43. SilkTextSizeH=1
  44. SilkTextSizeThickness=0.15
  45. SilkTextItalic=0
  46. SilkTextUpright=1
  47. CopperLineWidth=0.2
  48. CopperTextSizeV=1.5
  49. CopperTextSizeH=1.5
  50. CopperTextThickness=0.3
  51. CopperTextItalic=0
  52. CopperTextUpright=1
  53. EdgeCutLineWidth=0.05
  54. CourtyardLineWidth=0.05
  55. OthersLineWidth=0.15
  56. OthersTextSizeV=1
  57. OthersTextSizeH=1
  58. OthersTextSizeThickness=0.15
  59. OthersTextItalic=0
  60. OthersTextUpright=1
  61. SolderMaskClearance=0.051
  62. SolderMaskMinWidth=0.25
  63. SolderPasteClearance=0
  64. SolderPasteRatio=-0
  65. [pcbnew/Layer.F.Cu]
  66. Name=F.Cu
  67. Type=0
  68. Enabled=1
  69. [pcbnew/Layer.In1.Cu]
  70. Name=In1.Cu
  71. Type=1
  72. Enabled=1
  73. [pcbnew/Layer.In2.Cu]
  74. Name=In2.Cu
  75. Type=1
  76. Enabled=1
  77. [pcbnew/Layer.In3.Cu]
  78. Name=In3.Cu
  79. Type=0
  80. Enabled=0
  81. [pcbnew/Layer.In4.Cu]
  82. Name=In4.Cu
  83. Type=0
  84. Enabled=0
  85. [pcbnew/Layer.In5.Cu]
  86. Name=In5.Cu
  87. Type=0
  88. Enabled=0
  89. [pcbnew/Layer.In6.Cu]
  90. Name=In6.Cu
  91. Type=0
  92. Enabled=0
  93. [pcbnew/Layer.In7.Cu]
  94. Name=In7.Cu
  95. Type=0
  96. Enabled=0
  97. [pcbnew/Layer.In8.Cu]
  98. Name=In8.Cu
  99. Type=0
  100. Enabled=0
  101. [pcbnew/Layer.In9.Cu]
  102. Name=In9.Cu
  103. Type=0
  104. Enabled=0
  105. [pcbnew/Layer.In10.Cu]
  106. Name=In10.Cu
  107. Type=0
  108. Enabled=0
  109. [pcbnew/Layer.In11.Cu]
  110. Name=In11.Cu
  111. Type=0
  112. Enabled=0
  113. [pcbnew/Layer.In12.Cu]
  114. Name=In12.Cu
  115. Type=0
  116. Enabled=0
  117. [pcbnew/Layer.In13.Cu]
  118. Name=In13.Cu
  119. Type=0
  120. Enabled=0
  121. [pcbnew/Layer.In14.Cu]
  122. Name=In14.Cu
  123. Type=0
  124. Enabled=0
  125. [pcbnew/Layer.In15.Cu]
  126. Name=In15.Cu
  127. Type=0
  128. Enabled=0
  129. [pcbnew/Layer.In16.Cu]
  130. Name=In16.Cu
  131. Type=0
  132. Enabled=0
  133. [pcbnew/Layer.In17.Cu]
  134. Name=In17.Cu
  135. Type=0
  136. Enabled=0
  137. [pcbnew/Layer.In18.Cu]
  138. Name=In18.Cu
  139. Type=0
  140. Enabled=0
  141. [pcbnew/Layer.In19.Cu]
  142. Name=In19.Cu
  143. Type=0
  144. Enabled=0
  145. [pcbnew/Layer.In20.Cu]
  146. Name=In20.Cu
  147. Type=0
  148. Enabled=0
  149. [pcbnew/Layer.In21.Cu]
  150. Name=In21.Cu
  151. Type=0
  152. Enabled=0
  153. [pcbnew/Layer.In22.Cu]
  154. Name=In22.Cu
  155. Type=0
  156. Enabled=0
  157. [pcbnew/Layer.In23.Cu]
  158. Name=In23.Cu
  159. Type=0
  160. Enabled=0
  161. [pcbnew/Layer.In24.Cu]
  162. Name=In24.Cu
  163. Type=0
  164. Enabled=0
  165. [pcbnew/Layer.In25.Cu]
  166. Name=In25.Cu
  167. Type=0
  168. Enabled=0
  169. [pcbnew/Layer.In26.Cu]
  170. Name=In26.Cu
  171. Type=0
  172. Enabled=0
  173. [pcbnew/Layer.In27.Cu]
  174. Name=In27.Cu
  175. Type=0
  176. Enabled=0
  177. [pcbnew/Layer.In28.Cu]
  178. Name=In28.Cu
  179. Type=0
  180. Enabled=0
  181. [pcbnew/Layer.In29.Cu]
  182. Name=In29.Cu
  183. Type=0
  184. Enabled=0
  185. [pcbnew/Layer.In30.Cu]
  186. Name=In30.Cu
  187. Type=0
  188. Enabled=0
  189. [pcbnew/Layer.B.Cu]
  190. Name=B.Cu
  191. Type=0
  192. Enabled=1
  193. [pcbnew/Layer.B.Adhes]
  194. Enabled=1
  195. [pcbnew/Layer.F.Adhes]
  196. Enabled=1
  197. [pcbnew/Layer.B.Paste]
  198. Enabled=1
  199. [pcbnew/Layer.F.Paste]
  200. Enabled=1
  201. [pcbnew/Layer.B.SilkS]
  202. Enabled=1
  203. [pcbnew/Layer.F.SilkS]
  204. Enabled=1
  205. [pcbnew/Layer.B.Mask]
  206. Enabled=1
  207. [pcbnew/Layer.F.Mask]
  208. Enabled=1
  209. [pcbnew/Layer.Dwgs.User]
  210. Enabled=1
  211. [pcbnew/Layer.Cmts.User]
  212. Enabled=1
  213. [pcbnew/Layer.Eco1.User]
  214. Enabled=1
  215. [pcbnew/Layer.Eco2.User]
  216. Enabled=1
  217. [pcbnew/Layer.Edge.Cuts]
  218. Enabled=1
  219. [pcbnew/Layer.Margin]
  220. Enabled=1
  221. [pcbnew/Layer.B.CrtYd]
  222. Enabled=1
  223. [pcbnew/Layer.F.CrtYd]
  224. Enabled=1
  225. [pcbnew/Layer.B.Fab]
  226. Enabled=1
  227. [pcbnew/Layer.F.Fab]
  228. Enabled=1
  229. [pcbnew/Layer.Rescue]
  230. Enabled=0
  231. [pcbnew/Netclasses]
  232. [pcbnew/Netclasses/Default]
  233. Name=Default
  234. Clearance=0.127
  235. TrackWidth=0.1524
  236. ViaDiameter=0.8
  237. ViaDrill=0.4
  238. uViaDiameter=0.3
  239. uViaDrill=0.1
  240. dPairWidth=0.2
  241. dPairGap=0.25
  242. dPairViaGap=0.25